No Fault Found: The Root Cause

No Trouble Found (NTF) has been discussed for several years [1]. An NTF occurs when a device fails at the board/system level and that failure cannot be confirm by the component supplier. There are several explanations for why NTFs occur, including: device complexity; inability to create system level hardware/software transactions which uncover hard to find defects; different environments during testing (power, thermal, noise). More recently a new concept, No Fault Found (NFF), has emerged. A NFF represents a defect which cannot be detected by any known means so far. The premise is that at some point the defect will be exposed - most likely at a customer site when the device is in a system. Given that we looking for a defect that we know nothing about and are theoretically undetectable it will be interesting to see what the panel has to say about the nature of these defects and how we intend to find them

Re-using Chip Level DFT at Board Level

As chips are getting increasingly complex, there is no surprise to find more and more built-in DFX. This built-in DFT is obviously beneficial for chip/silicon DFX engineers; however, board/system level DFX engineers often have limited access to the build in DFX features. There is currently an increasing demand from board/system level DFX engineers to reuse chip/silicon DFX at board/system level. This special session will discuss: What chip access is needed for board-level for test and diagnosis? How to accomplish the access? Will IEEE P1687 and IEEE 1149.1 solve these problems

Learning digital test and diagnostics via Internet

An environment targeted to e-learning is presented for teaching design and test of electronic systems. The environment consists of a set of Java applets, and of web based access to the hardware equipments, which can be used in the classroom, for learning at home, in laboratory research and training, or for carrying out testing of students during exams. The tools support university courses on digital electronics, computer hardware, testing and design for testability to learn by hands-on exercises how to design digital systems, how to make them testable, how to build self-testing systems, how to generate test patterns, how to analyze the quality of tests, and how to localize faults in hardware. The tasks chosen for hands-on training represent simultaneously research problems, which allow to fostering in students critical thinking, problem solving skills and creativity

Parallel Fault Backtracing for Calculation of Fault Coverage

An improved method for calculation of fault coverage with parallel fault backtracing in combinational circuits is proposed. The method is based on structurally synthesized BDDs (SSBDD) which represent gate-level circuits at higher, macro level where macros represent subnetworks of gates. A topological analysis is carried out to generate an efficient model for backtracing of faults to minimize the repeated calculations because of the reconvergent fanouts. The algorithm is equivalent to exact critical path tracing. Because of the parallelism and higher abstraction level modeling the speed of analysis was considerably increased. Experimental data show that the speed-up of the new method is considerable compared to the previous similar approach. The speed of the fault analysis in several times outperforms the speed of the current state-of-the-art commercial fault simulators. 1